HT'ing

[Franklinwallbrown]

I didn't know where to put this, so...but I figured there are lots of people in here, so my question would get answered.

What exactly is HT'ing?

[DanTheBanjoman]

I guess you're referring to HyperThreading. It's a form of SMT. It allows idle parts of a CPU to execute an additional thread. It shows up as an additional processor in taskmanager and the likes, however it is far less efficient than having an actual additional core.

[Mussels]

if you knew what the abbreviation stood for it would help us narrow it down - i think dan guessed it however.

[erocker]

Both AMD and Intel have a bus speed, for example mine is set at 300 with a x10 multiplier on my cpu which makes 3ghz. Intel uses a "rated FSB" which is the bus speed times the bus multiplier. Amd calls it "HT link" which is pretty much the same thing. Example: FSB=200 x 4 (bus miltiplier) = 800 "fsb" or "ht link"

[Mussels]

Hyperthreading (intels early dual core CPU's)
Hypertransport (what Erocker was talking about, AMD's version of an FSB)

i'm sure theres others.

[DanTheBanjoman]

Hyperthreading (intels early dual core CPU's)

Has nothing to do with dual cores. There is only one core, they didn't duplicate anything. It's SMT, not SMP.

[btarunr]

HyperTransport is not something that belongs to AMD or something that's exclusive to it. It merely is a new bus topology. HyperTransport has an established SIG lead by the likes of AMD and NVidia.

The nForce series chipset (for both AMD and Intel processors) incorporates HyperTransport as its chipset bus (communication between the northbridge and southbridge)

There's nothing that I know of HT'ing having something to do with HyperTransport. The most sane guess is Hyperthreading. HT is neither an official nor casual abbreviation for HyperTransport after the confusion that erupted between that and Intel HT. So HT points to HyperThreading, a SMP technique. Ordinary single thread CPU's take in a linear stream of instructions and data to compute them. You can imagine a single core CPU with HT to be a French Juggler that splits CPU time at a very elementary level to deal with two simultaneous threads.

A "thread", apart from forum jargon:D is a logically assembled stream of of instructions and data. Instructions tell the processor what to do with the data and data, well you know.

[Mussels]

Has nothing to do with dual cores. There is only one core, they didn't duplicate anything. It's SMT, not SMP.

i was keeping it simple for the OP. sorry if it wasnt well received. (i actually edited the post after i originally made it, to make it simpler)

[Franklinwallbrown]

Thanks guys. So, AMD has some fast FSB's at 2k, wow.

[Mussels]

Its kinda weird - someone may explain it better than me, this is just how i see it.

AMD's FSB is 200 - its then pumped up to 1000 (2000 in DDR terms)

Intel use 200/266/333 on their latest, which are quad pumped (800/1066/1333)

Thats just what i know, i dont really know why its that way however.

[btarunr]

Its kinda weird - someone may explain it better than me, this is just how i see it.

AMD's FSB is 200 - its then pumped up to 1000 (2000 in DDR terms)

Intel use 200/266/333 on their latest, which are quad pumped (800/1066/1333)

Thats just what i know, i dont really know why its that way however.

NAW mate,

200 MHz is its Internal bus speed = FSB = True

But each clock-cycle of this bus takes in 2 instructions meaning 2 x 200 = 400 (effective) x DDR. in one direction of HyperTransport lanes. x 2 directions

1000 is not a clockrate, it's the measure of the efficiency of this bus, it's 1000 MT/s not MHz

MT/s = Million Transfers per second. :)

[Mussels]

thanks... like i said, i wasnt sure how it worked for AMD.

[btarunr]

thanks... like i said, i wasnt sure how it worked for AMD.

Beats me too mate. Their art of complicating things is a put-off. Classic example: 2900 XT

[Franklinwallbrown]

Whatever that means.

[Mandown]

NAW mate,

200 MHz is its Internal bus speed = FSB = True

But each clock-cycle of this bus takes in 2 instructions meaning 2 x 200 = 400 (effective) x DDR. in one direction of HyperTransport lanes. x 2 directions

1000 is not a clockrate, it's the measure of the efficiency of this bus, it's 1000 MT/s not MHz

MT/s = Million Transfers per second. :)

I'm pretty sure it is 1000 MHz and 2000 MT/s for AMD. and i read that HT just mostly helps system stability, is that correct?