Intel Announces Floating Body Cell Memory.

[Polaris573]

Intel announced today that it has made scaled Floating Body Cell (FBC) memory with its High-k and Metal Gate 45nm technology that could mean a new era of super dense cache cells in CPUs and other applications. FBC memory will allow three to four times greater memory density than standard SRAM cache. FBC uses just one capacitor while SRAM uses six transistors further decreasing the needed size. The FBC is on a single 45nm Metal Gate on a thin 22nm, ultra low voltage Silicon On Insulator (SOI) substrate. The device is two generations ahead of the one Intel showcased in 2006.

http://www.techpowerup.com/img/08-06-17/1_thm.jpg (http://www.techpowerup.com/img/08-06-17/1.jpg)http://www.techpowerup.com/img/08-06-17/2_thm.jpg (http://www.techpowerup.com/img/08-06-17/2.jpg)

Source: bit-tech (http://www.bit-tech.net/news/2008/06/17/intel-floats-bodies-in-new-kind-of-cache-memory/1)

[WarEagleAU]

sounds like a winner. Probably will lower costs a tad bit. I wonder if AMD will be able to "license" this architecture?

[PVTCaboose1337]

Neat concept... I just need to understand how it works.... To wikipedia!

[Mussels]

3x to 4x the cache... from 8MB to 32MB, weeeeee.