sweeper
11-24-2005, 03:05 PM
My card is a Retail BBA Radeon 9800 Pro with the 9800 Pro PCB and R360 core. It has Samung 2.8ns memory. It's being cooled with an Arctic Cooler vers.3 and OCZ Copper BGA Ramsinks. When flashed to an XT it cannot handle the XT speeds so I want to put a 9800 Bios back on the card since there is no reason to have the XT bios considering it does nothing but set the clocks higher in which I have to bring them down.
Just curious as to which bios would be better suited for my card. Being used, it came with the following bios reported by RaBit:
-- RaBiT v.1.5.0 build 320 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x10A
> PCIR struct offs: 0x178
> CRC table offs: 0x199
> CLOCK table offs: 0x8F4
Core clock is 378.00 MHz
Memory clock is 338.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1D9
MEM info: MC_CNTL(0x00000022), memory size = 128 Mb
> Memory config: 0x2240
> TV table offs: 0xC4FC
Active TV type: 'NTSC'
> DFP table offs: 0x63E
DFP table Ver.4, 2 preset(s)
TMDS_PLL(000B01CB), freq = 155.00 MHz
TMDS_PLL(000B01CB), freq = 200.00 MHz
> Connectors Layout table offs: 0x636
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x90
-- ROM BIOS info --
Desc: RADEON 9800 113-A07533-100 BIOS
Info: R350AGP DGD1UN, nhrq4593.815 v611 , 2003/10/17 14:33
Radeon family: Radeon 9800 series
-- Parsing hardware scripts: --
> PLL script at 0x053B
> PLL2 script at 0x05E5
> INIT script at 0x028D
> MEMORY script at 0x03C6
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x01383204) at 0x0565
> SCLK_CNTL(0x00000002) at 0x05AB
> MCLK_CNTL(0xAA3F1212) at 0x0594
> MC_TIMING_CNTL(0x1A19A222) at 0x040A
> MC_CNTL(0x00000022) at 0x03C8
> MC_SDRAM_MODE_REG(0x30420042) at 0x0420
> MC_CHP_IO_OE_CNTL_CD(0x4F304F30) at 0x0404
> MC_READ_CNTL_CD(0x399B399B) at 0x02FD
> MC_READ_CNTL_AB(0x399B399B) at 0x02F1
> MC_REFRESH_CNTL(0x00004029) at 0x02EB
> MC_CHP_IO_OE_CNTL_AB(0x4F304F30) at 0x03F8
-- In BIOS memory timings --
tWL = 1.0
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 5
tRcdWR = 3
tRP = 5
tRAS = 10
tRRD = 4
tR2W = CL + 3
tWR = 2
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 29
tRFC = 17
tRBS = CL + 2.5
tERST = CL - 1.5
tQSREQ = CL - 1.5
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = As specified
tDQS_Adv = As specified
-- Additional hardware SDRAM info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/2
SDRAM specific: 2**12 rows, 256 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --
________________________________
Or I have this BIOS which I'm not sure is any better or not but it's named different:
-- RaBiT v.1.5.0 build 320 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x10E
> PCIR struct offs: 0x17C
> CRC table offs: 0x19D
> CLOCK table offs: 0x8FE
Core clock is 378.00 MHz
Memory clock is 338.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1DD
MEM info: MC_CNTL(0x00000022), memory size = 128 Mb
> Memory config: 0x2240
> TV table offs: 0xC640
Active TV type: 'NTSC'
> DFP table offs: 0x653
DFP table Ver.4, 2 preset(s)
TMDS_PLL(000B01CB), freq = 155.00 MHz
TMDS_PLL(000B01CB), freq = 200.00 MHz
> Connectors Layout table offs: 0x64B
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x90
-- ROM BIOS info --
Desc: R360 Hynix DDR 113-A07537-103 BIOS
Info: R360AGP DGD1UN, nhrq6356.p03 v611 , 2004/03/04 09:51
Radeon family: Radeon 9800 series
-- Parsing hardware scripts: --
> PLL script at 0x053F
> PLL2 script at 0x05F0
> INIT script at 0x0291
> MEMORY script at 0x03CA
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x01383204) at 0x0569
> SCLK_CNTL(0x00000002) at 0x05B6
> MCLK_CNTL(0xAA3F1212) at 0x059F
> MC_TIMING_CNTL(0x1A29A222) at 0x040E
> MC_CNTL(0x00000022) at 0x03CC
> MC_SDRAM_MODE_REG(0x30430042) at 0x0424
> MC_CHP_IO_OE_CNTL_CD(0x5F305F30) at 0x0408
> MC_READ_CNTL_CD(0x39AC39AC) at 0x0301
> MC_READ_CNTL_AB(0x39AC39AC) at 0x02F5
> MC_REFRESH_CNTL(0x00004029) at 0x02EF
> MC_CHP_IO_OE_CNTL_AB(0x5F305F30) at 0x03FC
-- In BIOS memory timings --
tWL = 1.5
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 5
tRcdWR = 3
tRP = 5
tRAS = 10
tRRD = 4
tR2W = CL + 3
tWR = 3
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 29
tRFC = 17
tRBS = CL + 3
tERST = CL - 1
tQSREQ = CL - 1.5
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = As specified
tDQS_Adv = As specified
-- Additional hardware SDRAM info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/2
SDRAM specific: 2**12 rows, 256 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --
Just curious as to which bios would be better suited for my card. Being used, it came with the following bios reported by RaBit:
-- RaBiT v.1.5.0 build 320 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x10A
> PCIR struct offs: 0x178
> CRC table offs: 0x199
> CLOCK table offs: 0x8F4
Core clock is 378.00 MHz
Memory clock is 338.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1D9
MEM info: MC_CNTL(0x00000022), memory size = 128 Mb
> Memory config: 0x2240
> TV table offs: 0xC4FC
Active TV type: 'NTSC'
> DFP table offs: 0x63E
DFP table Ver.4, 2 preset(s)
TMDS_PLL(000B01CB), freq = 155.00 MHz
TMDS_PLL(000B01CB), freq = 200.00 MHz
> Connectors Layout table offs: 0x636
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x90
-- ROM BIOS info --
Desc: RADEON 9800 113-A07533-100 BIOS
Info: R350AGP DGD1UN, nhrq4593.815 v611 , 2003/10/17 14:33
Radeon family: Radeon 9800 series
-- Parsing hardware scripts: --
> PLL script at 0x053B
> PLL2 script at 0x05E5
> INIT script at 0x028D
> MEMORY script at 0x03C6
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x01383204) at 0x0565
> SCLK_CNTL(0x00000002) at 0x05AB
> MCLK_CNTL(0xAA3F1212) at 0x0594
> MC_TIMING_CNTL(0x1A19A222) at 0x040A
> MC_CNTL(0x00000022) at 0x03C8
> MC_SDRAM_MODE_REG(0x30420042) at 0x0420
> MC_CHP_IO_OE_CNTL_CD(0x4F304F30) at 0x0404
> MC_READ_CNTL_CD(0x399B399B) at 0x02FD
> MC_READ_CNTL_AB(0x399B399B) at 0x02F1
> MC_REFRESH_CNTL(0x00004029) at 0x02EB
> MC_CHP_IO_OE_CNTL_AB(0x4F304F30) at 0x03F8
-- In BIOS memory timings --
tWL = 1.0
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 5
tRcdWR = 3
tRP = 5
tRAS = 10
tRRD = 4
tR2W = CL + 3
tWR = 2
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 29
tRFC = 17
tRBS = CL + 2.5
tERST = CL - 1.5
tQSREQ = CL - 1.5
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = As specified
tDQS_Adv = As specified
-- Additional hardware SDRAM info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/2
SDRAM specific: 2**12 rows, 256 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --
________________________________
Or I have this BIOS which I'm not sure is any better or not but it's named different:
-- RaBiT v.1.5.0 build 320 --
> RaBiT driver v.1.0.5 is loaded
Readed from file: 53248 bytes, ROM len: 53248 bytes
-- Analyze ROM BIOS --
> HEADER offs: 0x10E
> PCIR struct offs: 0x17C
> CRC table offs: 0x19D
> CLOCK table offs: 0x8FE
Core clock is 378.00 MHz
Memory clock is 338.00 MHz
Reference clock is 27.00 MHz
> DRAM table offs: 0x1DD
MEM info: MC_CNTL(0x00000022), memory size = 128 Mb
> Memory config: 0x2240
> TV table offs: 0xC640
Active TV type: 'NTSC'
> DFP table offs: 0x653
DFP table Ver.4, 2 preset(s)
TMDS_PLL(000B01CB), freq = 155.00 MHz
TMDS_PLL(000B01CB), freq = 200.00 MHz
> Connectors Layout table offs: 0x64B
Conn0 type = VGA, DDC = VGA, DAC = Unknown
Conn1 type = DVI-I, DDC = DVI, DAC = Primary
ASIC init: 0x75 = 0x08, 0x74 = 0x90
-- ROM BIOS info --
Desc: R360 Hynix DDR 113-A07537-103 BIOS
Info: R360AGP DGD1UN, nhrq6356.p03 v611 , 2004/03/04 09:51
Radeon family: Radeon 9800 series
-- Parsing hardware scripts: --
> PLL script at 0x053F
> PLL2 script at 0x05F0
> INIT script at 0x0291
> MEMORY script at 0x03CA
-- Found hardware registers values: --
> M_SPLL_REF_FB_DIV(0x01383204) at 0x0569
> SCLK_CNTL(0x00000002) at 0x05B6
> MCLK_CNTL(0xAA3F1212) at 0x059F
> MC_TIMING_CNTL(0x1A29A222) at 0x040E
> MC_CNTL(0x00000022) at 0x03CC
> MC_SDRAM_MODE_REG(0x30430042) at 0x0424
> MC_CHP_IO_OE_CNTL_CD(0x5F305F30) at 0x0408
> MC_READ_CNTL_CD(0x39AC39AC) at 0x0301
> MC_READ_CNTL_AB(0x39AC39AC) at 0x02F5
> MC_REFRESH_CNTL(0x00004029) at 0x02EF
> MC_CHP_IO_OE_CNTL_AB(0x5F305F30) at 0x03FC
-- In BIOS memory timings --
tWL = 1.5
tCL = 4
tCMD = 0 clock
tSTB = equals tWrL
tRcdRD = 5
tRcdWR = 3
tRP = 5
tRAS = 10
tRRD = 4
tR2W = CL + 3
tWR = 3
tW2R = 2
tW2Rsb = Use tWR Rule
tR2R = 2
MemRR = 29
tRFC = 17
tRBS = CL + 3
tERST = CL - 1
tQSREQ = CL - 1.5
tDQM = WL - 1
tDQS = WL - 1
tDQM_Adv = As specified
tDQS_Adv = As specified
-- Additional hardware SDRAM info --
SDRAM Mode Register: 0x42
MCLK source select: MPLLCLK/2
SCLK source select: SPLLCLK/2
SDRAM specific: 2**12 rows, 256 columns
SDRAM dynamic CKE is Enabled
-- User changes followed --